Gate Delay Estimation in STA under Dynamic Power Supply Noise. | 0 | 0.34 | 2010 |
Gate delay estimation in STA under dynamic power supply noise | 14 | 1.24 | 2010 |
A Minimum Decap Allocation Technique Based On Simultaneous Switching For Nanoscale Soc | 1 | 0.37 | 2009 |
An Integrated Timing And Dynamic Supply Noise Verification For Multi-10-Million Gate Soc Designs | 1 | 0.56 | 2006 |
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias | 8 | 0.82 | 2005 |
Power-Supply Noise Reduction with Design for Manufacturability | 0 | 0.34 | 2005 |
Dynamic Power-Supply And Well Noise Measurements And Analysis For Low Power Body Biased Circuits | 4 | 0.88 | 2005 |
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs | 8 | 1.19 | 2005 |
A Substrate Noise Analysis Methodology For Large-Scale Mixed-Signal Ics | 9 | 1.82 | 2003 |
LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator | 6 | 0.95 | 2000 |