Yung Chia Lin - Citegraph

Author Info

Name	Affiliation	Papers
YUNG CHIA LIN	The National Tsing Hua University, Hsinchu, Taiwan	13
Collaborators	Citations	PageRank
26	58	7.69
Referers	Referees	References
115	277	160

Search Limit

100277

Publications (13 rows)

Collaborators (26 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Case Study: Support OpenCL Complex Class for Baseband Computing	0	0.34	2019
Guest Editorial: Special Issue on Embedded Multicore Applications and Optimization.	0	0.34	2019
LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files	12	0.69	2009
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores	3	0.41	2008
An MILP-based wire spreading algorithm for PSM-aware layout modification	2	0.39	2008
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch	9	0.62	2008
Palf: Compiler Supports For Irregular Register Files In Clustered Vliw Dsp Processors	6	0.48	2007
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains	3	0.38	2007
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors	5	0.60	2006
System-level design space exploration for security processor prototyping in analytical approaches	1	0.42	2005
Compiler supports and optimizations for PAC VLIW DSP processors	12	2.23	2005
Power-Aware scheduling for parallel security processors with analytical models	2	0.38	2004
Compiler optimizations with DSP-Specific semantic descriptions	3	0.43	2002

1