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FRANCESCO MENICHELLI
Author Info
Open Visualization
Name
Affiliation
Papers
FRANCESCO MENICHELLI
Univ Roma La Sapienza, Dept Elect Telecomm & Informat Eng, Rome, Italy
22
Collaborators
Citations
PageRank
33
255
15.93
Referers
Referees
References
681
316
111
Search Limit
100
681
Publications (22 rows)
Collaborators (33 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores
3
0.46
2021
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment
0
0.34
2020
Quality Aware Selective ECC for Approximate DRAM.
0
0.34
2019
Full System Emulation Of Approximate Memory Platforms With Appropinquo
0
0.34
2019
Quality Aware Approximate Memory in RISC-V Linux Kernel
0
0.34
2019
Approximate Memory Support for Linux Early Allocators in ARM Architectures.
0
0.34
2018
Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing.
1
0.35
2018
AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space
0
0.34
2018
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores
1
0.39
2017
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes.
2
0.44
2017
An Emulator for Approximate Memory Platforms Based on QEmu
0
0.34
2016
Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide
0
0.34
2015
A Model-Based Methodology to Generate Code for Timer Units
0
0.34
2014
A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems
0
0.34
2014
Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications.
0
0.34
2013
Delay-Tolerant, Low-Power Protocols For Large Security-Critical Wireless Sensor Networks
3
0.55
2012
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores.
1
0.35
2011
TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction.
4
0.38
2010
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips
9
0.59
2008
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
150
5.58
2005
A class of code compression schemes for reducing power consumption in embedded microprocessor systems
21
0.99
2004
A post-compiler approach to scratchpad mapping of code
60
2.12
2004
1
