Name
Title | ||
|---|---|---|
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. |
Abstract | ||
|---|---|---|
Internet-of-Things end-nodes demand low power processing platforms characterized by heterogeneous dedicated units, controlled by a processor core running multiple control threads. Such architecture scheme fits one of the main target application domain of the RISC-V instruction set. We present an open-source processing core compliant with RISC-V on the software side and with the popular Pulpino processor platform on the hardware side, while supporting interleaved multi-threading for IoT applications. The latter feature is a novel contribution in this application domain. We report details about the microarchitecture design along with performance data. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1007/978-3-319-93082-4_12 | ApplePies |
DocType | Volume | Citations |
Conference | abs/1712.04902 | 2 |
PageRank | References | Authors |
0.44 | 2 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abdallah Cheikh | 1 | 2 | 0.44 |
| Gianmarco Cerutti | 2 | 2 | 0.44 |
| Antonio Mastrandrea | 3 | 23 | 6.24 |
| Francesco Menichelli | 4 | 255 | 15.93 |
| Mauro Olivieri | 5 | 385 | 36.09 |