| A Normalized Figure of Merit for Capacitive Accelerometer Interface Circuits | 0 | 0.34 | 2020 |
| A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach. | 0 | 0.34 | 2019 |
| A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach | 0 | 0.34 | 2019 |
| A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance | 0 | 0.34 | 2018 |
| A Simplified Model for Passive-Switched-Capacitor Filters With Complex Poles. | 0 | 0.34 | 2016 |
| A Flexible Charge-Balanced Ratiometric Open-Loop Readout System for Capacitive Inertial Sensors | 1 | 0.40 | 2015 |
| An Open Source Inertial Sensor Network With Bluetooth Smart | 0 | 0.34 | 2015 |
| A pseudo-differential charge balanced ratiometric readout system for capacitive inertial sensors | 0 | 0.34 | 2015 |
| Charge-pump based switched-capacitor gain stage | 0 | 0.34 | 2012 |
| Incremental data converters at low oversampling ratios | 4 | 0.43 | 2010 |
| A Low-Power Capacitive Charge Pump Based Pipelined ADC | 20 | 1.08 | 2010 |
| A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps | 4 | 0.68 | 2009 |
| A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator | 18 | 2.19 | 2009 |
| A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator. | 0 | 0.34 | 2008 |
| An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage | 32 | 2.01 | 2008 |
| Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators | 1 | 0.41 | 2008 |
| A robust 4-PAM signaling scheme for inter-chip links using coding in space | 1 | 0.40 | 2008 |
| A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold. | 0 | 0.34 | 2007 |
| Coding schemes for chip-to-chip interconnect applications | 2 | 0.45 | 2006 |
| A Low-Power Crosstalk-Insensitive Signaling Scheme For Chip-To-Chip Communication | 1 | 0.37 | 2004 |
| A power-efficient architecture for high-speed D/A converters | 1 | 0.41 | 2003 |
| Digital Lms Adaptation Of Analog Filters Without Gradient Information | 5 | 0.69 | 2003 |
| A 5th order Gm-C filter in 0.25 μm CMOS with digitally programmable poles and zeroes | 4 | 2.30 | 2002 |
| Analog filter adaptation using a dithered linear search algorithm | 3 | 3.01 | 2002 |
| A differential 160-MHz self-terminating adaptive CMOS line driver | 4 | 0.82 | 2000 |
| Obtaining Digital Gradient Signals For Analog Adaptive Filters | 3 | 0.46 | 1999 |
| An integrated 200-MHz 3.3-V BiCMOS class-IV partial-response analog Viterbi decoder | 7 | 0.96 | 1998 |
| Stable One-Bit Delta-Sigma Modulators Based On Switching Control | 1 | 0.43 | 1998 |
| An Approach For Tuning High-Q Continuous-Time Bandpass Filters | 3 | 3.80 | 1995 |
| DC Offset Performance of Four LMS Adaptive Algorithms | 0 | 0.34 | 1994 |
| Equalization and linearization via linear negative feedback | 0 | 0.34 | 1993 |
| Adaptive IIR filtering of delta-sigma modulated signals | 0 | 0.34 | 1993 |
| On the Effect of Comparator Hysteresis in Interpolative Delta Sigma Modulators | 0 | 0.34 | 1993 |
| Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering | 1 | 0.88 | 1993 |
