Paper Info
Title
An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage
Abstract
A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is pre- sented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10 clock cycles.
Year
DOI
Venue
2008
10.1109/JSSC.2008.923724
Solid-State Circuits, IEEE Journal of
Keywords
Field
DocType
CMOS integrated circuits,analogue-digital conversion,calibration,digital-analogue conversion,error correction,pipeline processing,CMOS process,DAC error correction,analogue-digital conversion,calibration,digital background scheme,digital-analogue conversion,multibit pipeline stage,pipelined ADC,size 0.18 mum,voltage 1.8 V,word length 11 bit,ADC,CMOS,DAC,analog-to-digital conversion,background,calibration,capacitor mismatch,dual-ADC,missing codes,pipeline,rapid,split-ADC
Capacitor,Computer science,Electronic engineering,Spurious-free dynamic range,Cmos process,Error detection and correction,CMOS,Coding (social sciences),Calibration,Least significant bit
Journal
Volume
Issue
ISSN
43
7
0018-9200
Citations 
PageRank 
References 
32
2.01
11
Authors
2
Name
Order
Citations
PageRank
Ahmed, I.1412.90
David A. Johns211626.91