Author Info
Name
Affiliation
Papers
KOICHI NOSE
Institute of Industrial Science, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, 153-8505 Japan
15
Collaborators
Citations 
PageRank 
47
172
25.74
Referers 
Referees 
References 
499
133
36
Search Limit
100499
Title
Citations
PageRank
Year
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2.00.342019
Session 16 overview: Emerging technologies enabling next-generation systems: Technology directions subcommittee00.342015
F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels00.342015
A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme292.552012
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing.20.402010
On-Chip Optical Interconnect30.552009
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing40.532009
A 0.016 mm<formula formulatype="inline"><tex>$^{2}$</tex> </formula>, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis10.352008
Lsi On-Chip Optical Interconnection With Si Nano-Photonics50.502008
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops.272.462007
A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling131.742006
Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology10.352002
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools81.362001
Optimization of VDD and VTH for low-power and high speed applications7513.432000
Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)40.512000