Author Info
Name
Affiliation
Papers
JUERGEN TEICH
ETH Zurich, Swiss Fed Inst Technol, TIK, Comp Engn & Commun Networks Lab, CH-8092 Zurich, Switzerland
41
Collaborators
Citations 
PageRank 
104
90
18.01
Referers 
Referees 
References 
214
849
331
Search Limit
100849
Title
Citations
PageRank
Year
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains00.342022
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability *10.362021
Fault-Tolerant Low-Precision DNNs using Explainable AI00.342021
Approximate Logic Synthesis of Very Large Boolean Networks.00.342021
Enforcement FSMs – Specification and Verification of Non-Functional Properties of Program Executions on MPSoCs00.342021
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows20.372021
*-Predictable Mpsoc Execution Of Real-Time Control Applications Using Invasive Computing00.342021
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays00.342021
Choice – A Tunable PUF-Design for FPGAs10.352021
LION: Real-Time I/O Transfer Control for Massively Parallel Processor Arrays00.342021
Aarith: an arbitrary precision number library10.362021
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements00.342021
Symbolic Loop Compilation for Tightly Coupled Processor Arrays10.352021
HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids00.342020
Clustering-Based Scenario-Aware LTE Grant Prediction00.342020
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations00.342020
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays10.352020
A runtime system for finite element methods in a partitioned global address space00.342020
Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems.00.342020
SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide.00.342020
Energy Minimization in DAG Scheduling on MPSoCs at Run-Time - Theory and Practice.00.342020
Hard real-time application mapping reconfiguration for NoC-based many-core systems10.362019
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays00.342019
Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures00.342019
Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems00.342019
IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of Embedded Systems00.342019
Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and Its Application to Mobile Devices.00.342019
Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization10.352019
Anytime instructions for programmable accuracy floating-point arithmetic20.382019
Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures.110.482018
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning.00.342017
Automatic operating point distillation for hybrid mapping methodologies.30.382017
Auto-vectorization for image processing DSLs.10.372017
FPGA-Based Dynamically Reconfigurable SQL Query Processing.70.442016
Multi-objective local-search optimization using reliability importance measuring60.502014
Analysis of SystemC actor networks for efficient synthesis70.522010
Maintaining Virtual Areas on FPGAs using Strip Packing with Delays20.422010
No-Break Dynamic Defragmentation of Reconfigurable00.342010
A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs211.672009
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter111.652000
Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures.100.911998