Making Biased DL Models Work: Message and Key Recovery Attacks on Saber Using Amplitude-Modulated EM Emanations. | 0 | 0.34 | 2022 |
FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level. | 0 | 0.34 | 2022 |
FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level | 0 | 0.34 | 2022 |
Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations. | 0 | 0.34 | 2022 |
Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers | 0 | 0.34 | 2022 |
Side-Channel Analysis of the Random Number Generator in STM32 MCUs | 0 | 0.34 | 2022 |
Side-Channel Attacks on Lattice-Based KEMs Are Not Prevented by Higher-Order Masking. | 0 | 0.34 | 2022 |
Advanced Far Field EM Side-Channel Attack on AES | 0 | 0.34 | 2021 |
Multi-Source Training Deep-Learning Side-Channel Attacks | 0 | 0.34 | 2020 |
Breaking ACORN at Bitstream Level | 0 | 0.34 | 2020 |
Tandem Deep Learning Side-Channel Attack Against FPGA Implementation of AES | 1 | 0.41 | 2020 |
Breaking ACORN with a Single Fault. | 0 | 0.34 | 2019 |
How Diversity Affects Deep-Learning Side-Channel Attacks | 0 | 0.34 | 2019 |
Threshold Physical Unclonable Functions | 0 | 0.34 | 2019 |
A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks | 1 | 0.36 | 2018 |
Lightweight Message Authentication for Constrained Devices. | 0 | 0.34 | 2018 |
Comparison of CRC and KECCAK Based Message Authentication for Resource-Constrained Devices | 0 | 0.34 | 2018 |
On Designing PUF-Based TRNGs with Known Answer Tests | 1 | 0.36 | 2018 |
Message Authentication Based on Cryptographically Secure CRC without Polynomial Irreducibility Test. | 0 | 0.34 | 2018 |
One-Sided Countermeasures for Side-Channel Attacks Can Backfire. | 0 | 0.34 | 2018 |
Mvl-Pufs: Multiple-Valued Logic Physical Unclonable Functions | 3 | 0.40 | 2017 |
TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches | 1 | 0.39 | 2017 |
Reliable low-overhead arbiter-based physical unclonable functions for resource-constrained IoT devices. | 0 | 0.34 | 2017 |
Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST. | 0 | 0.34 | 2017 |
Protecting IMSI and User Privacy in 5G Networks | 0 | 0.34 | 2016 |
A SAT-Based Algorithm for Finding Short Cycles in Shift Register Based Stream Ciphers. | 0 | 0.34 | 2016 |
Physical Unclonable Functions based on Temperature Compensated Ring Oscillators. | 1 | 0.36 | 2016 |
Error-Correcting Message Authentication for 5G | 0 | 0.34 | 2016 |
On Constructing Secure and Hardware-Efficient Invertible Mappings | 0 | 0.34 | 2015 |
CRC-Based Message Authentication for 5G Mobile Technology | 7 | 0.49 | 2015 |
A random access procedure based on tunable puzzles | 0 | 0.34 | 2015 |
A scan partitioning algorithm for reducing capture power of delay-fault LBIST | 0 | 0.34 | 2015 |
Cryptographically Secure CRC for Lightweight Message Authentication. | 0 | 0.34 | 2015 |
Lightweight CRC-based Message Authentication. | 1 | 0.37 | 2015 |
An Equivalence-Preserving Transformation of Shift Registers. | 2 | 0.36 | 2014 |
Keyed logic BIST for Trojan detection in SoC | 5 | 0.44 | 2014 |
Synthesis of power- and area-efficient binary machines for incompletely specified sequences | 1 | 0.35 | 2014 |
Secure and efficient LBIST for feedback shift register-based cryptographic systems | 3 | 0.44 | 2014 |
Energy-efficient message authentication for IEEE 802.15.4-based wireless sensor networks | 0 | 0.34 | 2014 |
An Algorithm for Constructing a Minimal Register with Non-linear Update Generating a Given Sequence | 1 | 0.34 | 2014 |
Secure Key Storage Using State Machines | 1 | 0.36 | 2013 |
On-chip area-efficient binary sequence storage | 1 | 0.35 | 2013 |
A Scalable Method for Constructing Galois NLFSRs with Period 2n-1 using Cross-Join Pairs. | 0 | 0.34 | 2013 |
Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures | 0 | 0.34 | 2013 |
Embedding of Deterministic Test Data for In-Field Testing | 0 | 0.34 | 2013 |
A Faster Shift Register Alternative to Filter Generators | 0 | 0.34 | 2013 |
A BDD-Based Method for LFSR Parallelization with Application to Fast CRC Encoding. | 1 | 0.36 | 2013 |
An Improved Hardware Implementation of the Quark Hash Function. | 0 | 0.34 | 2013 |
An Algorithm for Constructing a Smallest Register with Non-Linear Update Generating a Given Binary Sequence. | 1 | 0.35 | 2013 |
An improved hardware implementation of the grain-128a stream cipher | 7 | 0.84 | 2012 |