Title
On-chip area-efficient binary sequence storage
Abstract
On-chip storage of binary sequences normally require the use of Read-Only Memories (ROMs). However, ROMs do not exploit of the fact that the stored information is accessed sequentially. This paper presents an area-efficient sequence storage technique based on state machines. Experimental results show that the presented method significantly outperforms previous approaches. The resulting state machines are on average 54% smaller than ROMs storing the same sequence.
Year
DOI
Venue
2013
10.1145/2483028.2483124
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
on-chip storage,read-only memories,state machine,resulting state machine,binary sequence,accessed sequentially,area-efficient sequence storage technique,previous approach,on-chip area-efficient binary sequence,cryptography,rom,lfsr
Linear feedback shift register,Cryptography,Computer science,Pseudorandom binary sequence,Electronic engineering,Exploit,Finite-state machine,Binary number,Built-in self-test
Conference
Citations 
PageRank 
References 
1
0.35
3
Authors
2
Name
Order
Citations
PageRank
Nan Li140.76
Elena Dubrova228848.55