| TinBiNN: Tiny Binarized Neural Network Overlay in about 5, 000 4-LUTs and 5mW. | 0 | 0.34 | 2019 |
| Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration | 0 | 0.34 | 2019 |
| Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories | 0 | 0.34 | 2018 |
| Automated Space/Time Scaling of Streaming Task Graph. | 1 | 0.37 | 2016 |
| Modular Switched Multiported SRAM-Based Memories. | 3 | 0.46 | 2016 |
| A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs | 2 | 0.39 | 2016 |
| Modular SRAM-Based Binary Content-Addressable Memories | 3 | 0.46 | 2015 |
| Rapid Overlay Builder for Xilinx FPGAs | 3 | 0.50 | 2015 |
| Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors | 0 | 0.34 | 2015 |
| Deep and narrow binary content-addressable memories using FPGA-based BRAMs | 3 | 0.47 | 2014 |
| Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor | 4 | 0.44 | 2013 |
| ZUMA: An Open FPGA Overlay Architecture | 37 | 1.55 | 2012 |
| Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. | 2 | 0.37 | 2012 |
| Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew | 6 | 0.65 | 2012 |
| Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations | 1 | 0.38 | 2011 |
| Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition | 8 | 0.57 | 2011 |
| Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs) | 5 | 0.42 | 2011 |
| VEGAS: soft vector processor with scratchpad memory | 35 | 1.85 | 2011 |
| Estimating reliability and throughput of source-synchronous wave-pipelined interconnect | 3 | 0.40 | 2009 |
| PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess | 7 | 0.60 | 2009 |
| GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering | 16 | 0.81 | 2008 |
| On two-step routing for FPGAS | 31 | 2.05 | 1997 |
| Segmented Routing For Speed-Performance And Routability In Field-Programmable Gate Arrays | 9 | 0.89 | 1996 |
