Paper Info
Title
GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering
Abstract
This paper describes GlitchLess, a circuit-level technique for reducing power in field-programmable gate arrays (FPGAs) by eliminating unnecessary logic transitions called glitches. This is done by adding programmable delay elements to the logic blocks of the FPGA. After routing a circuit and performing static timing analysis, these delay elements are programmed to align the arrival times of the inputs of each lookup table (LUT), thereby preventing new glitches from being generated. Moreover, the delay elements also behave as filters that eliminate other glitches generated by upstream logic or off-chip circuitry. On average, the proposed implementation eliminates 87% of the glitching, which reduces overall FPGA power by 17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires little or no modifications to the routing architecture or computer-aided design (CAD) flow.
Year
DOI
Venue
2008
10.1109/TVLSI.2008.2001237
IEEE Trans. VLSI Syst.
Keywords
DocType
Volume
delay element,added circuitry,logic block,dynamic power minimization,index terms—field-programmable gate arrays fpgas,low- power,switching activity minimization.,programmable delay element,overall fpga area,overall fpga power,routing architecture,upstream logic,unnecessary logic,critical-path delay,edge alignment,minimization,static timing analysis,field programmable gate array,lookup table,field programmable gate arrays,critical path,computer aided design,low power electronics,indexing terms,chip
Journal
16
Issue
ISSN
Citations 
11
1063-8210
16
PageRank 
References 
Authors
0.81
19
3
Name
Order
Citations
PageRank
Julien Lamoureux114210.22
Guy G. F. Lemieux217914.96
Steven J. E. Wilton31154130.09