A Symbolic Algorithm for the Synthesis of Bounded Petri Nets | 15 | 0.95 | 2008 |
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications | 79 | 3.61 | 2006 |
Quasi-static scheduling of independent tasks for reactive systems | 16 | 2.75 | 2005 |
Coping with The Variability of Combinational Logic Delays | 28 | 1.69 | 2004 |
From Synchronous to Asynchronous: An Automatic Approach | 9 | 0.79 | 2004 |
Design Of Asynchronous Controllers With Delay Insensitive Interface | 0 | 0.34 | 2002 |
What is the cost of delay insensitivity? | 12 | 0.86 | 1999 |
Partial-scan delay fault testing of asynchronous circuits | 11 | 0.74 | 1998 |
Decomposition and technology mapping of speed-independent circuits using Boolean relations | 11 | 0.81 | 1997 |
Structural methods for the synthesis of speed-independent circuits | 0 | 0.34 | 1996 |
Analysis and identification of speed-independent circuits on an event model | 11 | 1.32 | 1994 |