Name
Abstract | ||
|---|---|---|
This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead and reasonable area and power overhead. We discuss various scenarios in which completion detection can be used to measure the delay of a synchronous circuit at fabrication time or at run time, and of an asynchronous circuit at run time. We conclude by showing, on a large set of benchmarks, the effectiveness of the proposed technique. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ICCD.2004.1347969 | ICCD |
Keywords | Field | DocType |
synchronous circuit,asynchronous circuit,guarantees low timing overhead,power overhead,combinational logic delays,fabrication time,combinational logic network,proposed technique,completion detection,dual-rail encoding,run time,combinational circuits,encoding,dynamic logic | Clock signal,Digital electronics,Boolean circuit,Sequential logic,Computer science,Logic optimization,Real-time computing,Combinational logic,Synchronous circuit,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
1063-6404 | 0-7695-2231-9 | 28 |
PageRank | References | Authors |
1.69 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jordi Cortadella | 1 | 1862 | 163.70 |
| Alex Kondratyev | 2 | 192 | 14.20 |
| L. Lavagno | 3 | 330 | 50.09 |
| C. Sotiriou | 4 | 28 | 1.69 |