| Low voltage testing for interconnect opens under process variations | 1 | 0.36 | 2012 |
| Testing Skew and Logic Faults in SoC Interconnects | 2 | 0.39 | 2008 |
| Design-for-test techniques for opens in undetected branches in CMOS latches and flip-flops | 1 | 0.36 | 2007 |
| Signal Integrity Verification using High Speed Monitors | 2 | 0.39 | 2004 |
| Technical Program Committee | 0 | 0.34 | 2004 |
