Savithri Sundareswaran - Citegraph

Author Info

Name	Affiliation	Papers
SAVITHRI SUNDARESWARAN	Freescale Semiconductor, Inc.	16
Collaborators	Citations	PageRank
30	190	16.84
Referers	Referees	References
409	286	160

Search Limit

100409

Publications (16 rows)

Collaborators (30 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating	0	0.34	2015
Total sensitivity based dfm optimization of standard library cells	6	0.67	2010
Characterization of sequential cells for constraint sensitivities	1	0.36	2009
Characterization of Standard Cells for Intra-Cell Mismatch Variations	13	0.89	2008
A timing methodology considering within-die clock skew variations	2	0.38	2008
Faster statistical cell characterization using adjoint sensitivity analysis	2	0.39	2008
Transistor-specific delay modeling for SSTA	3	0.47	2008
A novel technique for incremental analysis of on-chip power distribution networks	6	0.51	2007
On-chip decoupling capacitance and P/G wire co-optimization for dynamic noise	7	0.65	2007
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming	12	0.84	2006
Optimal placement of power supply pads and pins	10	0.63	2004
A stochastic approach To power grid analysis	27	1.31	2004
Impact of Low-Impedance Substrate on Power Supply Integrity	5	0.75	2003
Statistical delay computation considering spatial correlations	63	5.53	2003
Vectorless Analysis of Supply Noise Induced Delay Variation	30	2.46	2003
On the interaction of power distribution network with substrate	3	0.68	2001

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