Potential Of Using Block Floating Point Arithmetic In Asip-Based Gnss-Receivers | 1 | 0.43 | 2010 |
Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers | 1 | 0.91 | 2010 |
ASIP-eFPGA Architecture for Multioperable GNSS Receivers | 1 | 0.37 | 2008 |
Application-specific reconfigurable processors | 0 | 0.34 | 2008 |
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers | 2 | 0.54 | 2007 |
Application specific instruction processor based implementation of a GNSS receiver on an FPGA | 10 | 0.91 | 2006 |