Name
Title | ||
|---|---|---|
Application specific instruction processor based implementation of a GNSS receiver on an FPGA |
Abstract | ||
|---|---|---|
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in low-power, low-cost SoC for multioperable GNSS positioning is described, featuring sufficient computational power and flexibility. The central processing unit of the reconfigurable hardware macro is an ASIP accelerated by additional eFPGA and weakly configurable ASIC based co-processors. The different hardware building blocks (i.e. ASIP, eFPGA, ASIC) of the target architecture are motivated with state of the art GNSS receiver algorithms. To explore the design space of the target architecture and to develop appropriate partitioning cost functions a GNSS receiver testbed was realised on an FPGA board. The testbed utilises a programmable ASIP, designed and generated with the processor description language LISA, as a central processing unit. As a first accelerating co-processor the correlator was realised. Exemplary optimisations of the ASIP/co-processor architecture as well as the achieved improvements are described |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/DATE.2006.243749 | Design, Automation and Test in Europe, 2006. DATE '06. Proceedings |
Keywords | Field | DocType |
additional efpga,application specific instruction processor,reconfigurable hardware macro,different hardware building block,art gnss receiver algorithm,gnss receiver,co-processor architecture,programmable asip,multioperable gnss positioning,target architecture,central processing unit,coprocessors,acceleration,programmable logic devices,fpga,application specific integrated circuits,space exploration,system on chip,radio receivers,testing,logic design,hardware,reconfigurable hardware,field programmable gate arrays,processor architecture,cost function,satellite navigation | Central processing unit,Application-specific instruction-set processor,Computer architecture,System on a chip,Computer science,Parallel computing,Field-programmable gate array,Application-specific integrated circuit,Coprocessor,Reconfigurable computing,Programmable logic device | Conference |
Volume | ISSN | ISBN |
2 | 1530-1591 | 3-9810801-0-6 |
Citations | PageRank | References |
10 | 0.91 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Götz Kappen | 1 | 15 | 3.50 |
| T. G. Noll | 2 | 129 | 13.50 |