An application-aware load balancing strategy for network processors | 3 | 0.39 | 2010 |
An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs | 0 | 0.34 | 2009 |
A hardware packet re-sequencer unit for network processors | 6 | 0.48 | 2008 |
Network processors | 0 | 0.34 | 2008 |
A Processing Path Dispatcher in Network Processor MPSoCs | 1 | 0.38 | 2008 |
Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications | 7 | 0.66 | 2007 |
A Programmable Stream Processing Engine for Packet Manipulation in Network Processors | 2 | 0.46 | 2007 |
Reconfigurable Processing Units vs. Reconfigurable Interconnects | 0 | 0.34 | 2006 |