Name
Abstract | ||
|---|---|---|
Network Processors (NP) usually are designed as multiprocessor systems with parallel packet processing. This parallelism may lead to flows with packets out-of-order when leaving the NP system. But packet reordering has a bad impact on network performance, especially when using the dominating TCP protocol. In this paper, we describe a Hardware Re-Sequencer Unit for Network Processors. Incoming packets will be tagged in the ingress path, preserving the packet order with flow granularity. An Aggregation Unit reorders the packet flows in the egress path if needed. In contrast to most other solutions the way of the packet through the NP system is dispensable, which enlarges design freedom in terms of e.g. load balancing. After explaining the general concept, a SystemC model is presented. Simulation results are used for dimensioning and a proof of concept with real traffic traces. General aspects concerning the implementation are discussed. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1007/978-3-540-78153-0_8 | ARCS |
Keywords | Field | DocType |
packet order,packet flow,network processors,aggregation unit,incoming packet,hardware re-sequencer unit,np system,egress path,hardware packet re-sequencer unit,parallel packet processing,packet reordering,network processor,network performance,out of order,load balance,proof of concept | Packet segmentation,End-to-end delay,Packet analyzer,Computer science,Transmission delay,Network packet,Parallel computing,Packet loss,Real-time computing,Packet processing,Computer hardware,Packet generator | Conference |
Volume | ISSN | ISBN |
4934 | 0302-9743 | 3-540-78152-8 |
Citations | PageRank | References |
6 | 0.48 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael Meitinger | 1 | 19 | 3.38 |
| Rainer Ohlendorf | 2 | 31 | 4.42 |
| Thomas Wild | 3 | 124 | 25.65 |
| Andreas Herkersdorf | 4 | 703 | 88.32 |