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CHAU-CHIN HUANG
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Name
Affiliation
Papers
CHAU-CHIN HUANG
National Taiwan University, Taipei, Taiwan
12
Collaborators
Citations
PageRank
35
69
5.88
Referers
Referees
References
165
225
128
Search Limit
100
225
Publications (12 rows)
Collaborators (35 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Latch Clustering For Timing-Power Co-Optimization
0
0.34
2020
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs
1
0.35
2020
End-to-End Industrial Study of Retiming
1
0.40
2018
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.
8
0.66
2018
Graph-Based Logic Bit Slicing for Datapath-Aware Placement.
0
0.34
2017
Clock-aware placement for large-scale heterogeneous FPGAs.
2
0.37
2017
Timing-driven cell placement optimization for early slack histogram compression
3
0.40
2016
Detailed-Routing-Driven analytical standard-cell placement
9
0.56
2015
Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints
9
0.57
2015
Routability-Driven Blockage-Aware Macro Placement
8
0.53
2014
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs
8
0.56
2014
Routability-driven placement for hierarchical mixed-size circuit designs
20
0.81
2013
1