Name
Abstract | ||
|---|---|---|
A wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical methodologies for faster turnaround time. This paper presents a novel two-stage technique to effectively identify design hierarchies and guide placement for better wirelength and routability. To optimize wirelength and routability simultaneously during placement, a new analytical net-congestion-optimization technique is also proposed. Compared with the participating teams for the 2012 ICCAD Design Hierarchy Aware Routability-driven Placement Contest, our placer can achieve the best quality (both the average overflow and wirelength) and the best overall score (by additionally considering running time). |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1145/2463209.2488921 | DAC |
Keywords | Field | DocType |
optimisation,faster turnaround time,effective routability-driven placer,routability-driven placement,network routing,placement,guide placement,wirelength-driven placer,net-congestion-optimization technique,new analytical net-congestion-optimization technique,best quality,integrated circuit design,irresolvable routing-congested placement,iccad design hierarchy aware,better wirelength,routability,physical design,hierarchical mixed-size circuit designs,hierarchical mixed-size circuit design,novel two-stage technique | Computer science,Network routing,Electronic engineering,Placement,Real-time computing,Integrated circuit design,Turnaround time,Physical design,Hierarchy | Conference |
ISSN | Citations | PageRank |
0738-100X | 20 | 0.81 |
References | Authors | |
20 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Meng-Kai Hsu | 1 | 166 | 7.29 |
| Yi-Fang Chen | 2 | 36 | 1.90 |
| Chau-Chin Huang | 3 | 69 | 5.88 |
| Tung-Chieh Chen | 4 | 486 | 27.19 |
| Yao-Wen Chang | 5 | 3437 | 253.54 |