Using moderate inversion to optimize voltage gain, thermal noise, and settling time in two-stage CMOS amplifiers | 2 | 0.45 | 2012 |
All-CMOS subbandgap reference circuit operating at low supply voltage | 3 | 1.15 | 2011 |
An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS | 2 | 0.40 | 2009 |
A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications | 14 | 3.89 | 2004 |
A CAD methodology for optimizing transistor current and sizing in analog CMOS design | 27 | 6.16 | 2003 |
Re-interpreting the MOS transistor via the inversion coefficient and the continuum of g/sub ms//I/sub d/ | 3 | 0.51 | 2002 |
Design-Oriented Characterization of CMOS over the Continuum of Inversion Level and Channel Length | 8 | 2.03 | 2000 |
A micropower CMOS, direct-conversion, VLF receiver chip for magnetic-field wireless applications | 0 | 0.34 | 1998 |