Paper Info
Title
Using moderate inversion to optimize voltage gain, thermal noise, and settling time in two-stage CMOS amplifiers
Abstract
This paper describes the use of moderate inversion for selected MOS transistors in a two-stage CMOS amplifier to achieve high voltage gain, low thermal noise, and fast settling time at minimum power consumption. A detailed circuit analysis, implemented in a MATLAB design tool, is presented to find the optimal inversion level for MOS transistors. The analysis and design tool are illustrated for a fully differential, two-stage, 0.5-μm CMOS amplifier having voltage gain >; 80 dB, input-referred thermal noise voltage <; 6 nV/Hz1/2, gain bandwidth of 100 MHz, phase margin of 58°, and 0.1% settling time <; 15 ns for load capacitances of 6 pF and a supply voltage of 2.5 V. SPICE simulation results confirm that these specifications are achieved at a minimum supply current of 2.42 mA by operating first- and second-stage input transistors in moderate inversion compared to 3.82 mA for operation in strong inversion, resulting in a 37% decrease in power consumption.
Year
DOI
Venue
2012
10.1109/ISCAS.2012.6272056
ISCAS
Keywords
Field
DocType
spice simulation,settling time,cmos integrated circuits,load capacitances,bandwidth 100 mhz,voltage gain,power consumption,current 2.42 ma,amplifiers,circuit analysis,size 0.5 mum,mos transistors,moderate inversion,matlab design tool,thermal noise,supply voltage,network analysis,mosfet,voltage 2.5 v,two-stage cmos amplifiers,transistors,capacitance,gain,noise
Settling time,Computer science,Control theory,Voltage,Noise (electronics),CMOS,Electronic engineering,Phase margin,High voltage,Transistor,Electrical engineering,Amplifier
Conference
ISSN
ISBN
Citations 
0271-4302
978-1-4673-0218-0
2
PageRank 
References 
Authors
0.45
1
3
Name
Order
Citations
PageRank
Yi Yang120.45
D. M. Binkley25914.93
Changzhi Li319535.68