| A Unified Framework for Design Validation and Manufacturing Test | 21 | 2.92 | 1996 |
| Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking | 27 | 1.55 | 1996 |
| Verification of Circuits Described in VHDL through Extraction of Design Intent | 3 | 0.48 | 1994 |
| Probabilistic Evaluation of Online Checks in Fault-Tolerant Multiprocessor Systems | 3 | 0.44 | 1992 |
