Paper Info
Title
A Unified Framework for Design Validation and Manufacturing Test
Abstract
New approaches to address the difficult problems intest are necessary if its current status as a major bottleneckin the production of quality integrated circuitsis to be changed. In this paper we propose a newdirection for solving the test problem using powerfulmethods already employed for the formal verificationof large circuits. More specifically, we will discuss howabstraction techniques can assist conventional ATPGtools when attacking hard to detect faults. The sameabstractions can ...
Year
DOI
Venue
1996
10.1109/TEST.1996.557149
ITC
Keywords
DocType
ISBN
manufacturing test,design validation,unified framework,design for testability,manufacturing,abstractions,hardware description languages,integrated circuit design,production,coverage,formal verification,confidence,automatic test pattern generation,fault detection,logic design
Conference
0-7803-3541-4
Citations 
PageRank 
References 
21
2.92
11
Authors
3
Name
Order
Citations
PageRank
Dinos Moundanos112812.90
J. Abraham24905608.16
Yatin Vasant Hoskote3545.39