Name
Title | Citations | PageRank | Year |
|---|---|---|---|
| A 4.5-GHz 130-nm 32-kb L0 cache with a leakage-tolerant self reverse-bias bitline scheme | 15 | 0.75 | 2003 |
| A sub-130-nm conditional keeper technique | 72 | 11.36 | 2002 |
| A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file | 21 | 1.91 | 2002 |