H. P. Hofstee - Citegraph

Author Info

Name	Affiliation	Papers
H. P. HOFSTEE	IBM Research Division, Austin Research Laboratory, Austin, TX	17
Collaborators	Citations	PageRank
62	507	54.92
Referers	Referees	References
1522	392	93

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Publications (17 rows)

Collaborators (62 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Low Latency and High Throughput Write-Ahead Logging Using CAPI-Flash	0	0.34	2021
Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA	0	0.34	2020
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation	2	0.42	2020
In-memory database acceleration on FPGAs: a survey	0	0.34	2020
Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow	1	0.37	2019
A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model	0	0.34	2019
Refine and Recycle: A Method to Increase Decompression Parallelism	0	0.34	2019
CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra	0	0.34	2018
Analyzing In-Memory Hash Join: Granularity Matters.	0	0.34	2017
Understanding system design for big data workloads	3	0.63	2013
True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.	8	0.71	2013
Big data text-oriented benchmark creation for Hadoop	15	1.26	2013
Cell broadband engine processor vault security architecture	10	0.65	2007
Introduction to the cell multiprocessor	426	44.90	2005
Timed circuit verification using TEL structures	9	0.66	2001
Custom circuit design as a driver of microprocessor performance	21	1.92	2000
Designing for a gigahertz [guTS integer processor]	12	1.03	1998

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