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F. M. GONÇALVES
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Name
Affiliation
Papers
F. M. GONÇALVES
INESC, CEAUTL, IST, Apartado 10105, 1017 Lisboa Codex, Portugal
11
Collaborators
Citations
PageRank
22
129
12.99
Referers
Referees
References
228
172
140
Search Limit
100
228
Publications (11 rows)
Collaborators (22 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
0
0.34
2002
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System
5
0.57
2002
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level
7
0.58
2001
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
29
2.24
2001
Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems
5
0.51
1999
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems
15
1.40
1997
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs
7
0.65
1994
Physical DFT for High Coverage of Realistic Faults
18
1.52
1992
A methodology for testability enhancement at layout level
19
2.43
1991
IC Defects-Based Testability Analysis
23
2.38
1991
A strategy for testability enhancement at layout level
1
0.38
1990
1