Name
Abstract | ||
|---|---|---|
The purpose of this paper is to present a RTL design and test methodology allowing the identification of design errors and difficult to verify functional parts. Using novel RTL fault models (namely, for arithmetic and relational operators) and Testability Metrics, two approaches are combined: RTL DFT and TPG. The need to inject faults on implicit variables of the RTL description is analyzed. Testability metrics, based on RTL fault detection (also associated with implicit variables), are shown to exhibit high correlation with Defects Coverage, DC. This high correlation enables RTL tradeoff analysis, for different DFT solutions, or test pattern generation. The proposed methodology for TPG leads to high DC by exercising RTL dark corners in a multiple and unbiased way. The resulting test patterns are, in fact, loosely deterministic patterns, suitable for low-cost BIST implementation. The usefulness of the methodology is ascertained using the mixed-level VeriDOS fault simulation tool and benchmarks circuits. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1023/A:1014997610714 | Journal of Electronic Testing |
Keywords | Field | DocType |
RTL,TPG,DFT,fault modeling | Design for testing,Testability,Test method,System on a chip,System testing,Computer science,Real-time computing,Design methods,Electronic engineering,Relational operator,Electronic circuit | Journal |
Volume | Issue | ISSN |
18 | 2 | 1573-0727 |
ISBN | Citations | PageRank |
0-7695-1016-7 | 0 | 0.34 |
References | Authors | |
27 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marcelino B. Santos | 1 | 129 | 20.76 |
| F. M. Gonçalves | 2 | 129 | 12.99 |
| I. C. Teixeira | 3 | 163 | 20.29 |
| João Paulo Teixeira | 4 | 0 | 0.34 |
| Mb Santos | 5 | 0 | 0.34 |
| Fm Goncalves | 6 | 0 | 0.34 |
| Ic Teixeira | 7 | 0 | 0.34 |
| Jp Teixeira | 8 | 0 | 0.34 |