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K. TAKAARA
Author Info
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Name
Affiliation
Papers
K. TAKAARA
Logic Design Laboratory, The University of Aizu 965-8580 Japan JP
1
Collaborators
Citations
PageRank
2
0
0.34
Referers
Referees
References
0
0
0
Publications (1 rows)
Collaborators (2 rows)
Referers (0 rows)
Referees (0 rows)
Title
Citations
PageRank
Year
The efficiency of neuron-MOS transistors in threshold logic
0
0.34
1999
1