F3: Adaptive design techniques for energy efficiency | 0 | 0.34 | 2014 |
Split-Path Fused Floating Point Multiply Accumulate (FPMAC) | 4 | 0.53 | 2013 |
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. | 66 | 4.47 | 2012 |
A 2 Tb/S 6 4 Mesh Network For A Single-Chip Cloud Computer With Dvfs In 45 Nm Cmos | 51 | 1.86 | 2011 |
18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS | 5 | 0.55 | 2010 |
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. | 19 | 1.14 | 2010 |
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS | 12 | 1.14 | 2009 |
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores | 1 | 0.36 | 2008 |
Design Challenges in Sub-100nm High Performance Microprocessors | 0 | 0.34 | 2004 |