Name
Title | ||
|---|---|---|
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores |
Abstract | ||
|---|---|---|
This paper describes a unified PopCount/ BitScanForward/BitScanReverse datapath circuit designed for 2.1GHz operation with total power consumption of 6.5mW, targeted for 65nm 64-bit microprocessor execution cores. The unified datapath uses a hybrid 3:2 compressor-based Wallace tree to count the number of `1's in the 64-bit input, along with a novel encoding scheme that enables reuse of the same tree to identify the bit-location of the 1st set bit when scanning the input in the forward and reverse directions. This circuit thus combines the functions of 3 separate units, enabling 26% reduction in total energy and 20% lower area, while achieving single-cycle latency & throughput. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/VLSI.2008.75 | VLSI Design |
Keywords | Field | DocType |
bitscan datapath unit,high-performance microprocessor execution cores,unified datapath,total energy,64-bit microprocessor execution core,compressor-based wallace tree,64-bit unified popcount,64-bit input,lower area,total power consumption,unified popcount,separate unit,bitscanreverse datapath circuit,cmos integrated circuits,encoding,logic design,circuit design | Logic synthesis,Datapath,Computer science,Finite state machine with datapath,Microprocessor,Electronic engineering,CMOS,Real-time computing,Throughput,Wallace tree,Encoding (memory) | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-7695-3083-4 | 1 |
PageRank | References | Authors |
0.36 | 1 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajaraman Ramanarayanan | 1 | 113 | 8.34 |
| S. Mathew | 2 | 462 | 76.59 |
| Vasantha Erraguntla | 3 | 158 | 10.73 |
| Ram Krishnamurthy | 4 | 650 | 74.63 |
| Shay Gueron | 5 | 354 | 53.88 |