Author Info
Name
Papers
Collaborators
PARTHASARATHY, K.
2
5
Citations 
PageRank 
Referers 
1
0.96
2
Referees 
References 
7
4
Title
Citations
PageRank
Year
A methodology for architecture synthesis of cascaded IIR filters on TLU FPGAs00.341994
Architectural synthesis of performance-driven multipliers with accumulator interleaving10.631993