Name
Abstract | ||
|---|---|---|
In this paper, we propose an architecture synthe- sis methodolog 'to realize cascaded Infinite Impulse Response (IIRJfilter in Table Look Up (TLU) Field Progmmmable Gate Amys (FPGA). The synthesis procedure involves a systematic tmnsfomation of the Dependance Graph (DG) corresponding to the cas- caded IIR filter to a Papelined Fized Full Size A+ my (PFFSA). We ofler an implementation of a cas- caded 8th order IIR filters on Xilinz XC3090 FPGA devices. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/ICVD.1994.282690 | VLSI Design |
Keywords | Field | DocType |
VLSI,cascade networks,digital filters,digital signal processing chips,filtering and prediction theory,graph theory,logic arrays,pipeline processing,table lookup,8th order IIR filters,Xilinx XC3090 FPGA devices,architecture synthesis,cascaded IIR filters,dependance graph,field programmable gate arrays,infinite impulse response,pipelined fixed full size array,systematic transformation,table lookup FPGA | Graph theory,Graph,Architecture,Digital filter,Computer science,Infinite impulse response,Field-programmable gate array,Real-time computing,Electronic engineering,Supercomputer Education Research Centre,Very-large-scale integration | Conference |
ISSN | Citations | PageRank |
1063-9667 | 0 | 0.34 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rathna, G.N. | 1 | 0 | 0.34 |
| Nandy, S.K. | 2 | 43 | 7.29 |
| Parthasarathy, K. | 3 | 1 | 0.96 |