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T. TUAN
Author Info
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Name
Affiliation
Papers
T. TUAN
Xilinx Res Labs, 2100 Log Dr, San Jose, CA 95134 USA
13
Collaborators
Citations
PageRank
39
425
53.13
Referers
Referees
References
659
194
147
Search Limit
100
659
Publications (13 rows)
Collaborators (39 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
6
0.47
2008
A 90-nm Low-Power FPGA for Battery-Powered Applications
61
3.00
2007
Analysis Of Data Remanence In A 90nm Fpga
6
0.67
2007
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
10
0.50
2006
Thermal Characterization and Optimization in Platform FPGAs
16
0.93
2006
A 90nm low-power FPGA for battery-powered applications
71
3.67
2006
Heterogeneous routing architecture for low-power FPGA fabric
13
1.21
2005
Leakage control in FPGA routing fabric
17
1.57
2005
Challenges and opportunities for low power FPGAs in nanometer technologies
0
0.34
2005
Reducing leakage energy in FPGAs using region-constrained placement
81
4.65
2004
A Dual-VDD Low Power FPGA Architecture
48
2.23
2004
Leakage Power Analysis Of A 90nm Fpga
74
6.20
2003
Design methodology for PicoRadio networks
22
27.67
2001
1