Valerio Tenace - Citegraph

Author Info

Name	Affiliation	Papers
VALERIO TENACE	Politecnico Di Torino, Torino, Italy	15
Collaborators	Citations	PageRank
13	17	5.71
Referers	Referees	References
38	186	85

Search Limit

100186

Publications (15 rows)

Collaborators (13 rows)

Referers (38 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies.	2	0.39	2020
Energy-Efficient Convolutional Neural Networks Via Recurrent Data Reuse	0	0.34	2019
Layer-Wise Compressive Training for Convolutional Neural Networks.	1	0.38	2019
SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars	1	0.35	2019
Quasi-exact logic functions through classification trees.	0	0.34	2018
Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits	0	0.34	2018
Activation-Kernel Extraction through Machine Learning	0	0.34	2017
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs.	0	0.34	2016
Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture.	0	0.34	2016
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits	1	0.38	2016
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits	4	0.48	2015
Ultra-low power circuits using graphene p–n junctions and adiabatic computing	1	0.38	2015
Row-based body-bias assignment for dynamic thermal clock-skew compensation.	0	0.34	2014
Pass-XNOR logic: a new logic style for P-N junction based graphene circuits	5	0.59	2014
NBTI effects on tree-like clock distribution networks	2	0.40	2012

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