Name
Abstract | ||
|---|---|---|
A Memristor is a two-terminal device that can serve as a non-volatile memory element with built-in logic capabilities. Arranged in a crossbar structure, memristive arrays allow to represent complex Boolean logic functions that adhere to the logic-in-memory paradigm, where data and logic gates are glued together on the same piece of hardware. Needless to say, novel and ad-hoc CAD solutions are required to achieve practical and feasible hardware implementations. Existing techniques aim at optimal mapping strategies that account for Boolean logic functions described by means of 2-input NOR and NOT gates, thus overlooking the optimization capabilities that a smart and dedicated technology-aware logic synthesis can provide. In this paper, we introduce a novel library-free supergate-aided (SAID) logic synthesis approach with a dedicated mapping strategy tailored on MAGIC crossbars. Supergates are obtained with a Look-Up Table (LUT)-based synthesis that splits a complex logic network into smaller Boolean functions. Those functions are then mapped on the crossbar array as to minimize latency. The proposed SAID flow allows to (i) maximize supergate-level parallelism, thus reducing the total number of computing cycles, and (ii) relax mapping constraints, allowing an easy and fast mapping of Boolean functions on memristive crossbars. Experimental results obtained on several benchmarks from ISCAS'85 and IWLS'93 suites demonstrate that our solution is capable to outperform other state-of-the-art techniques in terms of speedup (3.89× in the best case), at the expense of a very low area overhead. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.23919/DATE.2019.8714939 | 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) |
Keywords | Field | DocType |
feasible hardware implementations,optimal mapping strategies,optimization capabilities,smart technology-aware logic synthesis,dedicated technology-aware logic synthesis,dedicated mapping strategy,MAGIC crossbars,supergates,Table-based synthesis,complex logic network,smaller Boolean functions,crossbar array,supergate-level parallelism,mapping constraints,memristive crossbars,supergate-aided logic synthesis flow,two-terminal device,nonvolatile memory element,logic capabilities,crossbar structure,memristive arrays,complex Boolean logic functions,logic-in-memory paradigm,logic gates,practical hardware implementations,library-free supergate-aided logic synthesis approach | Logic synthesis,Computer science,Parallel computing,Flow (psychology) | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-7281-0331-0 | 1 |
PageRank | References | Authors |
0.35 | 7 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Valerio Tenace | 1 | 17 | 5.71 |
| Roberto Giorgio Rizzo | 2 | 2 | 2.41 |
| Debjyoti Bhattacharjee | 3 | 26 | 9.84 |
| Anupam Chattopadhyay | 4 | 6 | 4.23 |
| Andrea Calimera | 5 | 293 | 38.89 |