E. Ostua - Citegraph

Author Info

Name	Affiliation	Papers
E. OSTUA	Departamento de Tecnología Electrónica de la Universidad de Sevilla, Escuela Técnica Superior de Ingeniería Informática, Sevilla, Spain	4
Collaborators	Citations	PageRank
16	4	1.58
Referers	Referees	References
15	50	22

Publications (4 rows)

Collaborators (16 rows)

Referers (15 rows)

Referees (50 rows)

Title	Citations	PageRank	Year
Long-term on-chip verification of systems with logical events scattered in time	1	0.43	2012
Static power consumption in CMOS gates using independent bodies	0	0.34	2007
Application of internode model to global power consumption estimation in SCMOS gates	1	0.38	2005
Internode: Internal Node Logic Computational Model	2	0.43	2003

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