Name
Abstract | ||
|---|---|---|
In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consider aspects like input collisions and internal power consumption. Also, we explain the importance of internal power consumption (such effect occurs when an input transition does not affect the output) in three different technologies (AMS 0.6 μm, AMS 0.35 μm, and UMC 130 nm). This consumption becomes more remarkable as technology advances yielding to underestimating up to 9.4% of global power consumption in the UMC 130 nm case. Finally, we show how to optimize power estimation in the SCMOS NOR-2 gate by applying Internode to modeling its consumption accurately. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/11556930_35 | PATMOS |
Field | DocType | Volume |
Logic gate,Electrical load,Computer science,Finite-state machine,Electronic engineering,Power consumption | Conference | 3728 |
ISSN | ISBN | Citations |
0302-9743 | 3-540-29013-3 | 1 |
PageRank | References | Authors |
0.38 | 7 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alejandro Millán Calderón | 1 | 2 | 0.77 |
| M. J. Bellido | 2 | 1 | 0.72 |
| Jorge Juan-chico | 3 | 31 | 6.52 |
| P. Ruiz-de-Clavijo | 4 | 5 | 1.19 |
| David Guerrero Martos | 5 | 1 | 0.38 |
| E. Ostua | 6 | 4 | 1.58 |
| J. Viejo | 7 | 3 | 2.65 |