| Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks | 0 | 0.34 | 2022 |
| Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC | 0 | 0.34 | 2021 |
| On Improving 5g Internet Of Radio Light Security Based On Led Fingerprint Identification Method | 0 | 0.34 | 2021 |
| Effect of Illumination Intensity on LED Based Visible Light Communication System | 0 | 0.34 | 2020 |
| Cryo-CMOS for Analog/Mixed-Signal Circuits and Systems | 0 | 0.34 | 2020 |
| The Synergy SPICE – Compact Models | 0 | 0.34 | 2019 |
| SPINE (SPIN Emulator) - A Quantum-Electronics Interface Simulator | 0 | 0.34 | 2019 |
| Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures | 1 | 0.36 | 2019 |
| PAPR reduction based on deep autoencoder for VLC DCO-OFDM system | 1 | 0.35 | 2019 |
| Cryo-CMOS Circuits and Systems for Quantum Computing Applications. | 18 | 1.63 | 2018 |
| Experimental 5G New Radio integration with VLC | 1 | 0.38 | 2018 |
| A Co-Design Methodology For Scalable Quantum Processors And Their Classical Electronic Interface | 0 | 0.34 | 2018 |
| Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited. | 3 | 0.49 | 2017 |
| 1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell. | 0 | 0.34 | 2017 |
| Process and temperature impact on single-event transients in 28nm FDSOI CMOS | 1 | 0.63 | 2017 |
| Tunnel FET based refresh-free-DRAM. | 0 | 0.34 | 2017 |
| Cryogenic CMOS interfaces for quantum devices | 0 | 0.34 | 2017 |
| Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition. | 0 | 0.34 | 2017 |
| TFET NDR skewed inverter based sensing method | 0 | 0.34 | 2016 |
| 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications | 0 | 0.34 | 2016 |
| A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI. | 3 | 0.44 | 2016 |
| Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications | 0 | 0.34 | 2016 |
| FDSOI and Bulk CMOS SRAM Cell Resilience to Radiation Effects. | 0 | 0.34 | 2016 |
| Modeling the impact of heavy ion on FDSOI NanoCMOS | 1 | 1.08 | 2015 |
| Ultra-Low Leakage Sub-32nm Tfet/Cmos Hybrid 32kb Pseudo Dual-Port Scratchpad With Ghz Speed For Embedded Applications | 4 | 0.54 | 2015 |
| Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes | 0 | 0.34 | 2015 |
| Bulk and FDSOI Sub-micron CMOS transistors resilience to single-event transients | 1 | 0.87 | 2015 |
| Design considerations for low-noise transconductance amplifiers in 28nm UTBB-FDSOI | 0 | 0.34 | 2015 |
| CMOS SRAM scaling limits under optimum stability constraints | 3 | 0.81 | 2013 |
| A 32nm Tunnel Fet Sram For Ultra Low Leakage | 0 | 0.34 | 2012 |
| Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization | 3 | 0.71 | 2012 |
| Sram Voltage And Current Sense Amplifiers In Sub-32nm Double-Gate Cmos Insensitive To Process Variations And Transistor Mismatch | 1 | 0.42 | 2009 |
| An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch. | 0 | 0.34 | 2008 |
| Numerical methods for simulation of guitar distortion circuits | 11 | 1.59 | 2008 |
| A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation | 6 | 1.16 | 2007 |
| Analog circuit synthesis using standard EDA tools | 2 | 0.42 | 2006 |
| Standby supply voltage minimization for deep sub-micron SRAM | 16 | 1.95 | 2005 |
| Modeling subthreshold SOI logic for static timing analysis | 6 | 0.98 | 2004 |
| SRAM leakage suppression by minimizing standby supply voltage | 73 | 15.98 | 2004 |
| Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems | 0 | 0.34 | 2002 |
