Yuejian Wu - Citegraph

Author Info

Name	Affiliation	Papers
YUEJIAN WU	Nortel Networks, POB 3511,Stn C, Ottawa, ON K1Y 4H7, Canada	23
Collaborators	Citations	PageRank
26	164	17.13
Referers	Referees	References
348	304	167

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100348

Publications (23 rows)

Collaborators (26 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs	0	0.34	2015
“Free” Razor: A novel adaptive voltage scaling low power technique for data path SoC designs	1	0.52	2012
Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC Designs	4	0.43	2011
Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC	0	0.34	2008
Low Power SoC Memory BIST	1	0.35	2006
Fast detection of data retention faults and other SRAM cell open defects	7	0.48	2006
SRAM retention testing: zero incremental time integration with March algorithms	1	0.38	2005
A retention-aware test power model for embedded SRAM	2	0.38	2005
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs	2	0.41	2005
Low power decoding of BCH codes	4	0.66	2004
Designs for reducing test time of distributed small embedded SRAMs	2	0.44	2004
Testing ASICs with multiple identical cores	12	0.80	2003
Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch	1	0.44	2002
Shadow write and read for at-speed BIST of TDM SRAMs	0	0.34	2001
Interconnect delay fault testing with IEEE 1149.1	2	0.40	1999
Scan-based BIST fault diagnosis	22	1.33	1999
Diagnosis of Scan Chain Failures	51	3.59	1998
Built-In Self-Test for Multi-Port RAMs	12	1.33	1997
BIST fault diagnosis in scan-based VLSI environments	24	1.70	1996
Reducing hardware with fuzzy multiple signature analysis	5	0.70	1995
Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST	3	0.56	1995
Minimal hardware multiple signature analysis for BIST	1	0.36	1993
Accelerated path delay fault simulation	7	0.86	1992