Name
Abstract | ||
|---|---|---|
This paper addresses the test power model problem for embedded SRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a "single-rectangle" power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of "zero" power consumption for the detection of Data Retention Faults. This paper takes advantage of this "zero" power period and proposes a "retention-aware" test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarious in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the "zero" power period is fully utilized in a SoC environment. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1120725.1120935 | ASP-DAC |
Keywords | Field | DocType |
maximum test time reduction,test time reduction,test time,test power model problem,retention-aware test power model,test power model,test algorithm complexity,retention test duration,test power consumption,embedded sram,e-sram test,power period,embedded systems,system on chip,scheduling | System on a chip,Data retention,Test algorithm,Scheduling (computing),Computer science,Electronic engineering,Static random-access memory,Power model,Real-time computing,Power consumption,Test power | Conference |
ISSN | ISBN | Citations |
2153-6961 | 0-7803-8737-6 | 2 |
PageRank | References | Authors |
0.38 | 15 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Baosheng Wang | 1 | 62 | 7.37 |
| Josh Yang | 2 | 28 | 3.03 |
| Yuejian Wu | 3 | 164 | 17.13 |
| André Ivanov | 4 | 193 | 16.71 |