C.E. Goutis - Citegraph

Author Info

Name	Affiliation	Papers
C.E. GOUTIS	VLSI Design Laboratory, Dept. of Electrical Eng., University of Patras, Greece	4
Collaborators	Citations	PageRank
7	2	1.41
Referers	Referees	References
3	24	12

Publications (4 rows)

Collaborators (7 rows)

Referers (3 rows)

Referees (24 rows)

Title	Citations	PageRank	Year
An efficient decomposition technique for mapping nested loops with constant dependencies into regular processor arrays	2	0.39	1992
Array processor for LS FIR system identification	0	0.34	1991
A placing and routing tool implemented in Prolog	0	0.34	1991
A generator for a number format conversion IC	0	0.34	1990

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