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T. UCHIKOBA
Author Info
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Name
Affiliation
Papers
T. UCHIKOBA
Syst. LSI Technol. Dev. Center, Corp. Syst. LSI Dev. Div., Kyoto, Japan
2
Collaborators
Citations
PageRank
30
1
0.82
Referers
Referees
References
19
8
2
Publications (2 rows)
Collaborators (30 rows)
Referers (19 rows)
Referees (8 rows)
Title
Citations
PageRank
Year
A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process
0
0.34
2005
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications
1
0.48
2001
1