Author Info
Name
Affiliation
Papers
SHAMSI AZMI
Central R&D, STMicroelectronics, Noida 201301 INDIA
2
Collaborators
Citations 
PageRank 
16
3
0.75
Referers 
Referees 
References 
8
51
12
Title
Citations
PageRank
Year
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.20.402017
Architecture and Design of a High Performance SRAM for SoC Design10.362002