A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. - Citegraph

Paper Info

Title
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.

Abstract
An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35-1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential supply and body modulation write assist scheme are proposed. We also propose a layout that reduces metal capacitance of wordlines by 54% and also enables b...

Year	DOI	Venue
2017	10.1109/TCSI.2017.2705116	IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords	Field	DocType
SRAM cells,Low voltage,Circuit stability,Layout,Logic gates	Logic gate,Capacitance,Process corners,Computer science,Voltage,Electronic engineering,CMOS,Static random-access memory,Low voltage,Memory cell	Journal
Volume	Issue	ISSN
64	9	1549-8328
Citations	PageRank	References
2	0.40	9
Authors
13

Authors (13 rows)

Cited by (2 rows)

References (9 rows)

Name	Order	Citations	PageRank
Anuj Grover	1	10	6.49
G. S. Visweswaran	2	45	10.68
Chittoor R. Parthasarathy	3	2	0.40
Mohammad Daud	4	2	0.40
D. Turgis	5	11	4.96
Bastien Giraud	6	53	17.41
Jean-Philippe Noël	7	23	7.54
Ivan Miro Panades	8	96	7.81
guillaume moritz	9	6	1.90
Edith Beigne	10	536	52.54
Philippe Flatresse	11	97	15.35
Promod Kumar	12	2	0.40
Shamsi Azmi	13	3	0.75

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