Jean-Olivier Plouchart

Author Info

Name	Affiliation	Papers
JEAN-OLIVIER PLOUCHART	IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA	21
Collaborators	Citations	PageRank
79	106	20.36
Referers	Referees	References
306	192	66

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100306

Publications (21 rows)

Collaborators (79 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams.	0	0.34	2022
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage	0	0.34	2020
Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions	0	0.34	2018
Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C.	3	0.38	2018
Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information	5	0.48	2015
Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits.	4	0.43	2014
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits	5	0.49	2014
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing	3	0.52	2013
An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS	1	0.48	2012
A 4gs/S, 8.45 Enob And 5.7fj/Conversion, Digital Assisted, Sampling System In 45nm Cmos Soi	1	0.37	2011
An 8-Bit 1.5gs/S Flash Adc Using Post-Manufacturing Statistical Selection	4	0.67	2010
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.	17	2.42	2009
An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS.	2	0.42	2009
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS	3	0.52	2008
Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS.	6	1.14	2007
Statistical framework for technology-model-product co-design and convergence	4	0.60	2007
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology	1	0.46	2007
A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS	13	1.47	2007
Frequency-independent equivalent-circuit model for on-chip spiral inductors	23	6.99	2003
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate	9	1.13	2003
A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology	2	0.37	2003