Speed Binning with Path Delay Test in 150-nm Technology | 60 | 4.06 | 2003 |
Fastpath: a path-delay test generator for standard scan designs | 43 | 3.73 | 1994 |
Path-delay fault simulation for a standard scan design methodology | 2 | 0.73 | 1994 |
The interdependence between delay-optimization of synthesized networks and testing | 40 | 9.97 | 1991 |
Delay Testing Quality in Timing-Optimized Designs | 17 | 2.95 | 1991 |
The Parallel-Test-Detect Fault Simulation Algorithm | 16 | 3.35 | 1989 |
D3FS: a demand driven deductive fault simulator | 0 | 0.34 | 1988 |
An Analysis of Parallel Logic Simulation on Several Architectures | 3 | 0.52 | 1988 |
Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm | 9 | 1.91 | 1986 |
Built-In Self Test Input Generator for Programmable Logic Arrays | 6 | 0.62 | 1985 |