Name
Abstract | ||
|---|---|---|
As CAD tools become more sophisticated, they can synthesize logic netivorks that more nearly optimize the circuit area resources to maximize operating speeds. In this work we show, through formal arguments, that the path delays in such optimized networks will follow a more compact distribution and, in the extreme in some networks, will all be equal to the m“mum delay through the network (cycle time). The impact of this type of synthesized network on delay testing will be shown and compared to the case for nonoptim”zed designs. Finally, recommendations will be made on how network tim”ng optimization can be abne in such a way as to minimize the adverse impact on product yield. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1145/127601.127633 | DAC |
Keywords | Field | DocType |
synthesized network,testing,design automation,routing,logic design,cycle time,network synthesis,productivity | Logic synthesis,Permission,Computer science,Network synthesis filters,Control engineering,Real-time computing,Electronic design automation | Conference |
ISBN | Citations | PageRank |
0-89791-395-7 | 40 | 9.97 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. W. Williams | 1 | 1049 | 194.23 |
| Bill Underwood | 2 | 196 | 28.17 |
| M. R. Mercer | 3 | 353 | 47.36 |